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document number: mc33910 rev. 4.0, 2/2008 freescale semiconductor advance information * this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? freescale semiconductor, in c., 2007. all rights reserved. lin system basis chip with 2x60ma high side drivers the 33910 is a serial peripheral interface (spi)-controlled system basis chip (sbc), that combines many frequently used functions in an mcu-based system, plus a local interconnect network (lin) transceiver. it has a 5.0v, 60ma low dropout regulator with full protection and reporting featur es. the device provides full spi- readable diagnostic and a selectable timing watchdog for detecting errant operation. the lin protoc ol specification, version 2.0 compliant lin transceiver has wave shaping circuitry that can be disabled for higher data rates. two 60ma high side switches with optional pulse-width modulation (pwm) are implemented to drive sm all loads. one high voltage input is available for use in contact monitoring or as external wake-up input. this input can be used as high vo ltage analog input as well. the voltage on this pin is divided by a selectable ratio and available via an analog multiplexer. the 33910 has three main operating modes: normal (all functions available); sleep (v dd off, wake-up via lin, wake-up input (l1), cyclic sense and forced wake-up) and stop (v dd on with limited current capability, wake-up via cs , lin bus, wake-up input, cyclic sense, forced wake-up and external reset). the 33910 is compatible with li n protocol specification 2.0. features ? two 60ma high side switches ? one high voltage analog/logic input ? full-duplex spi at frequencies up to 4mhz ? lin transceiver capable of up to 100kbps with wave shaping ? configurable window watchdog ? 5.0v low drop regulator with fault detection and low voltage reset (lvr) circuitry ? switched/protected 5.0v output (used for hall sensors) ? pb-free packaging designated by suffix code ac figure 1. 33910 simplified application diagram system basis chip with lin 2 nd generation 33910 ordering information device temperature range (t a ) package mc33910bac/r2 - 40c to 125c 32-lqfp mc34910bac/r2 - 40c to 85c ac suffix (pb-free) 98ash70029a 32-pin lqfp 33910 mcu lin interface vs1 vs2 vsense hs1 l1 hvdd hs2 wdconf agnd lgnd pgnd lin vdd pwmin adout0 mosi miso sclk cs rxd txd irq rst v bat
analog integrated circuit device data 2 freescale semiconductor 33910 internal block diagram internal block diagram figure 2. 33910 simplifi ed internal block diagram voltage regulator high side control module interrupt control module lvi, hvi, hti, oci reset control module lvr, hvr, htr, wd window watchdog module spi & control lin physical layer wake-up module digital input module analog input chip temperature sense module analog multiplexer module agnd pgnd hs1 l1 lin rst irq vs2 vs1 vdd pwmin miso mosi sclk cs adout0 rxd txd lgnd wdconf vs2 internal bus 5v output module hvdd hs2 vs2 v bat sense module vsense
analog integrated circuit device data freescale semiconductor 3 33910 pin connections pin connections figure 3. 33910 pin connections table 1. 33910 pin definitions a functional description of each pin can be found in the functional pin description section beginning on page 20 . pin pin name formal name definition 1 rxd receiver output this pin is the receiver output of the lin interface which reports the state of the bus voltage to the mcu interface. 2 txd transmitter input this pin is the transmitter input of the lin interface which controls the state of the bus output. 3 miso spi output spi data output. when cs is high, the pin is in the high-impedance state. 4 mosi spi input spi data input. 5 sclk spi clock spi clock input. 6 cs spi chip select spi chip select input pin. cs is active low. 7 adout0 analog output pin 0 analog multiplexer output. 8 pwmin pwm input high side pulse width modulation input. 9 rst internal reset i/o bidirectional reset i/o pin - driven lo w when any internal reset source is asserted. rst is active low. 10 irq internal interrupt output interrupt output pin, indicating wake-up events from stop mode or events from normal and normal request modes. irq is active low. 11, 15-17, 19-22, 28 nc no connect * special configuration recommended / mandatory for marked nc pins 8 pwmin 7 adout0 5 sclk 4 mosi 3 miso 1 rxd 2 txd 6 cs 17 nc* 18 pgnd 20 nc* 21 nc* 22 nc* 24 hs2 23 l1 19 nc* 25 hs1 26 vs2 28 nc 29 vsense 30 hvdd 32 agnd 31 vdd 27 vs1 16 15 rst 13 irq 12 wdconf 11 9 lin 10 lgnd 14 nc* nc* nc*
analog integrated circuit device data 4 freescale semiconductor 33910 pin connections 12 wdconf watchdog configuration pin this input pin is for configuration of the watchdog period and allows the disabling of the watchdog. 13 lin lin bus this pin represents the single-wire bus transmitter and receiver. 14 lgnd lin ground pin this pin is the device lin ground connecti on. it is internally connected to the pgnd pin. 18 pgnd power ground pin this pin is the device power ground connec tion. it is internally connected to the lgnd pin. 23 l1 wake-up input this pin is a wake-up capable digital input (1) . in addition, l1 can be sensed analog via the analog multiplexer. 24, 25 hs2, hs1 high side outputs high side switch outputs. 26, 27 vs2, vs1 power supply pin these pins are device battery level power supply pins. vs2 is supplying the hs1 driver while vs1 supplies the remaining blocks. (2) 29 vsense voltage sense pin battery voltage sense input. (3) 30 hvdd hall sensor supply output +5.0v switchable supply output pin. (4) 31 vdd voltage regulator output +5.0v main voltage regulator output pin. (5) 32 agnd analog ground pin this pin is the device analog ground connection. notes 1. when used as digital input, a series 33k ? resistor must be used to prot ect against automotive transients. 2. reverse battery protection series diodes must be us ed externally to protect the internal circuitry. 3. this pin can be connected directly to the battery line for vo ltage measurements. the pin is self protected against reverse ba ttery connections. it is strongly recommended to connect a 10k ? resistor in series with this pin for protection purposes. 4. external capacitor (1f < c < 10f; 0.1 ? < esr < 5 ? ) required. 5. external capacitor (2f < c < 100f; 0.1 ? < esr < 10 ? ) required. table 1. 33910 pin definitions a functional description of each pin can be found in the functional pin description section beginning on page 20 . pin pin name formal name definition
analog integrated circuit device data freescale semiconductor 5 33910 electrical characteristics maximum ratings electrical characteristics maximum ratings table 2. maximum ratings all voltages are with respect to grou nd, unless otherwise noted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit electrical ratings supply voltage at vs1 and vs2 normal operation (dc) transient conditions (load dump) v sup(ss) v sup(pk) -0.3 to 27 -0.3 to 40 v supply voltage at vdd v dd -0.3 to 5.5 v input / output pins voltage (6) cs , rst , sclk, pwmin, adout0, mosi, miso, txd, rxd interrupt pin (irq ) (7) v in v in(irq) -0.3 to v dd +0.3 -0.3 to 11 v hs1 pin voltage (dc) v hs1 - 0.3 to v sup +0.3 v hs2 pin voltage (dc) v hs2 - 0.3 to v sup +0.3 v l1 pin voltage normal operation with a series 33k ? resistor (dc) transient input voltage with external component (according to iso7637-2) (see figure 5 , page 16 ) v l1dc v l1tr -18 to 40 100 v vsense pin voltage (dc) v vsense -27 to 40 v lin pin voltage normal operation (dc) transient input voltage with external component (according to iso7637-2) (see figure 4 , page 16 ) v busdc v bustr -18 to 40 -150 to 100 v vdd output current i vdd internally limited a esd voltage (8) human body model - lin pin human body model - all other pins machine model charge device model corner pins (pins 1, 8, 9, 16, 17, 24, 25 and 32) all other pins (pins 2-7, 10-15, 18-23, 26-31) v esd1-1 v esd1-2 v esd2 v esd3-1 v esd3-2 8000 2000 200 750 500 v nc pin voltage (nc pins 11, 15, 16, 17, 19, 20, 21, 22, and 28) (9) v nc note 9 notes 6. exceeding voltage limits on spec ified pins may cause a malfunction or permanent damage to the device. 7. extended voltage range for programming purpose only. 8. testing is performed in accordanc e with the human body model (c zap = 100 pf, r zap = 1500 ?), the machine model (c zap = 200 pf, r zap = 0 ?), and the charge device model, robotic (c zap = 4.0pf ). 9. special configuration recommended / mandatory for marked nc pins. please refer to the typical application shown on page 40 .
analog integrated circuit device data 6 freescale semiconductor 33910 electrical characteristics maximum ratings thermal ratings operating ambient temperature (10) 33910 34910 t a -40 to 125 -40 to 85 c operating junction temperature (10) t j -40 to 150 c storage temperature t stg -55 to 150 c thermal resistance, junction to ambient natural convection, single layer board (1s) (11), (12) natural convection, four layer board (2s2p) (11), (13) r ja 85 56 c/w thermal resistance, junction to case (14) r jc 23 c/w peak package reflow temperature during reflow (15) , (16) t pprt note 16 c notes 10. the limiting factor is junction temperat ure; taking into account the power dissipat ion, thermal resistance, and heat sinking . 11. junction temperature is a function of on-chip power dissipat ion, package thermal resistance, mounting site (board) temperatu re, ambient temperature, air flow, power dissipation of othe r components on the board, and board thermal resistance. 12. per jedec jesd51-2 with the singl e layer board (jesd51-3) horizontal. 13. per jedec jesd51-6 with the board (jesd51-7) horizontal. 14. thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1 ). 15. pin soldering temperature limit is for 10 seconds maximum du ration. not designed for immersion soldering. exceeding these li mits may cause malfunction or permanent damage to the device. 16. freescale?s package reflow capability m eets pb-free requirements for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.free scale.com, search by part number [e.g. remove prefixes/suffixe s and enter the core id to view all orderable parts. (i.e. mc33xxxd enter 33xxx), and review parametrics. table 2. maximum ratings (continued) all voltages are with respect to grou nd, unless otherwise noted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit
analog integrated circuit device data freescale semiconductor 7 33910 electrical characteristics static electrical characteristics static electrical characteristics table 3. static electric al characteristics characteristics noted under conditions 5.5v v sup 18v, -40c t a 125c for the 33910 and -40c t a 85c for the 34910, unless otherwise not ed. typical values noted reflect th e approximate parameter mean at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit supply voltage range (vs1, vs2) nominal operating voltage v sup 5.5 ? 18 v functional operating voltage (17) v supop ? ? 27 v load dump v supld ? ? 40 v supply current range ( v sup = 13.5v) normal mode (i out at v dd = 10ma), lin recessive state (18) i run ? 4.5 10 ma stop mode, vdd on with i out = 100a, lin recessive state (18) , (19) , (20) 5.5v < v sup < 12v v sup = 13.5v i stop ? ? 48 58 80 90 a sleep mode, vdd off, lin recessive state (18) , (20) 5.5v < v sup < 12v 12v v sup < 13.5v i sleep ? ? 27 37 35 48 a cyclic sense supply current adder (21) i cyclic ? 10 ? a supply under/over-voltage detections power-on reset (batfail) (22) threshold (measured on vs1) (21) hysteresis (measured on vs1) (21) v batfail v batfail_hys 1.5 ? 3.0 0.9 3.9 ? v v sup under-voltage detection (vsuv flag) (normal and normal request modes, interrupt generated) threshold (measured on vs1) hysteresis (measured on vs1) v suv v suv_hys 5.55 ? 6.0 1.0 6.6 ? v v sup over-voltage detection (vsov flag) (normal and normal request modes, interrupt generated) threshold (measured on vs1) hysteresis (measured on vs1) v sov v sov_hys 18 ? 19.25 1.0 20.5 ? v notes 17. device is fully functional . all features are operating. 18. total current (i vs1 + i vs2 ) measured at gnd pins excluding all loads, cyclic sense disabled. 19. total i dd current (including loads) below 100a. 20. stop and sleep mode currents will increase if v sup exceeds13.5v. 21. this parameter is guaranteed by proc ess monitoring but, not production tested. 22. the flag is set during power up sequence. to clear the flag, a spi read must be performed.
analog integrated circuit device data 8 freescale semiconductor 33910 electrical characteristics static electrical characteristics voltage regulator (23) (vdd) normal mode output voltage 1.0ma < i vdd < 50ma; 5.5v < v sup < 27v v ddrun 4.75 5.00 5.25 v normal mode output current limitation i vddrun 60 110 200 ma dropout voltage (24) i vdd = 50ma v dddrop ? 0.1 0.25 v stop mode output voltage i vdd < 5ma v ddstop 4.75 5.0 5.25 v stop mode output current limitation i vddstop 6.0 12 36 ma line regulation normal mode, 5.5v < v sup < 18v; i vdd = 10ma stop mode, 5.5v < v sup < 18v; i vdd = 1.0ma lr run lr stop ? ? 20 5.0 25 25 mv load regulation normal mode, 1.0ma < i vdd < 50ma stop mode, 0.1ma < i vdd < 5ma ld run ld stop ? ? 15 10 80 50 mv over-temperature prewarning (junction) (25) interrupt generated, bit vddot set t pre 110 125 140 c over-temperature pre-warning hysteresis (25) t pre_hys ? 10 ? c over-temperature shutdown temperature (junction) (25) t sd 155 170 185 c over-temperature shutdown hysteresis (25) t sd_hys ? 10 ? c hall sensor supply output (26) (hvdd) v dd voltage matching h vddacc = (hvdd-vdd) / vdd * 100% i hvdd = 15ma h vddacc -2.0 ? 2.0 % current limitation i hvdd 20 30 50 ma dropout voltage i hvdd = 15ma; i vdd = 5ma h vdddrop ? 160 300 mv line regulation i hvdd = 5ma; i vdd = 5ma lr hvdd ? 25 40 mv load regulation 1ma > i hvdd > 15ma; i vdd = 5ma ld hvdd ? 10 20 mv notes 23. specification with external capacitor 2f < c < 100f and 100m ? esr 10 ?. 24. measured when voltage has dropped 250mv below its nominal value (5v). 25. this parameter is guaranteed by pr ocess monitoring but, not production tested. 26. specification with external capacitor 1f < c < 10f and 100m ? esr 10 ?. table 3. static electrical characteristics (continued) characteristics noted under conditions 5.5v v sup 18v, -40c t a 125c for the 33910 and -40c t a 85c for the 34910, unless otherwise not ed. typical values noted reflect th e approximate parameter mean at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 9 33910 electrical characteristics static electrical characteristics rst input/output pin (rst ) vdd low voltage reset threshold v rst th 4.3 4.5 4.7 v low-state output voltage i out = 1.5ma; 3.5v v sup 27v v ol 0.0 ? 0.9 v high-state output current (0 < v out < 3.5v) i oh -150 -250 -350 a pull-down current limitation (internally limited) v out = v dd i pd_max 1.5 ? 8.0 ma low-state input voltage v il -0.3 ? 0.3 x v dd v high-state input voltage v ih 0.7 x v dd ? v dd + 0.3 v miso spi output pin (miso) low-state output voltage i out = 1.5ma v ol 0.0 ? 1.0 v high-state output voltage i out = -250a v oh v dd - 0.9 ? v dd v tri-state leakage current 0 v v miso v dd i trimiso -10 ? 10 a spi input pins (mosi, sclk, cs ) low-state input voltage v il -0.3 ? 0.3 x v dd v high-state input voltage v ih 0.7 x v dd ? v dd + 0.3 v mosi, sclk input current 0 v in v dd i in -10 ? 10 a cs pull-up current 0 < v in < 3.5v i pucs 10 20 30 a interrupt output pin ( irq ) low-state output voltage i out = 1.5 ma v ol 0.0 ? 0.8 v high-state output voltage i out = -250a v oh v dd - 0.8 ? v dd v leakage current v dd v out 10 v v oh ? ? 2.0 ma pulse width modulation input pin (pwmin) low-state input voltage v il -0.3 ? 0.3 x v dd v high-state input voltage v ih 0.7 x v dd ? v dd + 0.3 v pull-up current 0 < v in < 3.5v i pupwmin 10 20 30 a table 3. static electrical characteristics (continued) characteristics noted under conditions 5.5v v sup 18v, -40c t a 125c for the 33910 and -40c t a 85c for the 34910, unless otherwise not ed. typical values noted reflect th e approximate parameter mean at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 10 freescale semiconductor 33910 electrical characteristics static electrical characteristics high side output hs1 and hs2 pins (hs1, hs2) output drain-to-source on resistance t j = 25c, i load = 50ma; v sup > 9.0v t j = 150c, i load = 50ma; v sup > 9.0v (27) t j = 150c, i load = 30ma; 5.5v < v sup < 9.0v (27) r ds(on) ? ? ? ? ? ? 7.0 10 14 ? output current limitation (28) 0v < v out < v sup - 2.0v i limhs1 60 120 250 ma open load current detection (29) i olhsx ? 5.0 7.5 ma leakage current (-0.2v < v hsx < v s2 + 0.2v) i leak ? ? 10 a short circuit detection threshold (30) 5.5v < v sup < 27v v thsc v sup - 2 ? ? v over-temperature shutdown (31) , (32) t hssd 150 165 180 c over-temperature shutdown hysteresis (32) t hssd_hys ? 10 ? c l1 input pin (l1) low detection threshold 5.5v < v sup < 27v v thl 2.0 2.5 3.0 v high detection threshold 5.5v < v sup < 27v v thh 3.0 3.5 4.0 v hysteresis 5.5v < v sup < 27v v hys 0.5 1.0 1.5 v input current (33) -0.2v < v in < vs1 i in -10 ? 10 a analog input impedance (34) r l1in 800 1550 ? k ? analog input divider ratio (ratio l1 = v l1 / v adout0 ) l1ds (l1 divider select) = 0 l1ds (l1 divider select) = 1 ratio l1 0.95 3.42 1.0 3.6 1.05 3.78 analog output offset ratio l1ds (l1 divider select) = 0 l1ds (l1 divider select) = 1 v ratiol1- offset -80 -22 0.0 0.0 80 22 mv analog inputs matching l1ds (l1 divider select) = 0 l1ds (l1 divider select) = 1 l1 matching 96 96 100 100 104 104 % notes 27. this parameter is production tested up to t a = 125c and guaranteed by process monitoring up to t j = 150c. 28. when over-current occurs, the high side stays on with li mited current capability and the hs1cl flag is set in the hssr . 29. when open-load occurs, the flag (hs1op) is set in the hssr . 30. when short circuit occurs and if hvse flag is enabled, hs1 automatic shutdown. 31. when over-temperature shutdown occurs, both high sides are turned off. all flags in hssr are set. 32. guaranteed by characterization but, not production tested 33. analog multiplexer input di sconnected from l1 input pin. 34. analog multiplexer input connected to l1 input pin. table 3. static electrical characteristics (continued) characteristics noted under conditions 5.5v v sup 18v, -40c t a 125c for the 33910 and -40c t a 85c for the 34910, unless otherwise not ed. typical values noted reflect th e approximate parameter mean at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 11 33910 electrical characteristics static electrical characteristics window watchdog configuration pin (wdconf) external resistor range r ext 20 ? 200 k ? watchdog period accuracy with extern al resistor (excluding resistor accuracy) (35) wd acc -15 ? 15 % analog multiplexer internal chip temperature sense gain s ttov ? 10.5 ? mv/k vsense input divider ratio (ratio vsense = v vsense / v adout0 ) 5.5v < v sup < 27v ratio vsense 5.0 5.25 5.5 vsense output related offset -40c < t a < -20c offset vsens e -30 -45 ? ? 30 45 mv analog output (adout0) maximum output voltage -5ma < i o < 5ma v out_max v dd - 0.35 ? v dd v minimum output voltage -5ma < i o < 5ma v out_min 0.0 ? 0.35 v rxd output pin (lin physical layer) (rxd) low-state output voltage i out = 1.5 ma v ol 0.0 ? 0.8 v high-state output voltage i out = -250a v oh v dd -0.8 ? v dd v txd input pin (lin physical layer) (txd) low-state input voltage v il -0.3 ? 0.3 x nv dd v high-state input voltage v ih 0.7 x v dd ? v dd + 0.3 v pin pull-up current, 0 < v in < 3.5v i puin 10 20 30 a notes 35. watchdog timing period ca lculation formula: t pwd [ms] = 0.466 * (r ext - 20) + 10 (r ext in k ?) table 3. static electrical characteristics (continued) characteristics noted under conditions 5.5v v sup 18v, -40c t a 125c for the 33910 and -40c t a 85c for the 34910, unless otherwise not ed. typical values noted reflect th e approximate parameter mean at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 12 freescale semiconductor 33910 electrical characteristics static electrical characteristics lin physical layer, transceiver (lin) (36) output current limitation dominant state, v bus = 18v i buslim 40 120 200 ma leakage output current to gnd dominant state; v bus = 0v; v bat = 12v recessive state; 8v < v bat < 18v; 8v < v bus < 18v; v bus v bat gnd disconnected; gnd device = v sup ; v bat = 12v; 0 < v bus < 18v v bat disconnected; v sup_device = gnd; 0 < v bus < 18v i bus_pas_dom i bus_pas_rec i bus_no_gnd i bus -1.0 ? -1.0 ? ? ? ? ? ? 20 1.0 100 ma a ma a receiver input voltages receiver dominant state receiver recessive state receiver threshold center (v th_dom + v th_rec )/2 receiver threshold hysteresis (v th_rec - v th_dom ) v busdom v busrec v bus_cnt v hys ? 0.6 0.475 ? ? ? 0.5 ? 0.4 ? 0.525 0.175 v sup lin transceiver output voltage recessive state, txd high, i out = 1.0 a dominant state, txd low, 500 ? external pull-up resistor, ldvs = 0 dominant state, txd low, 500 ? external pull-up resistor, ldvs = 1 v lin_rec v lin_dom_0 v lin_dom_1 v sup -1 ? ? ? 1.1 1.7 ? 1.4 2 v lin pull-up resistor to v sup r slave 20 30 60 k ? over-temperature shutdown (37) t linsd 150 165 180 c over-temperature shutdown hysteresis t linsd_hys ? 10 ? c notes 36. parameters guaranteed for 7.0v v sup 18v. 37. when over-temperature shutdown occurs, the lin bus goes in recessive state and the flag linot in linsr is set. table 3. static electrical characteristics (continued) characteristics noted under conditions 5.5v v sup 18v, -40c t a 125c for the 33910 and -40c t a 85c for the 34910, unless otherwise not ed. typical values noted reflect th e approximate parameter mean at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 13 33910 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 4. dynamic electri cal characteristics characteristics noted under conditions 5.5v v sup 18v, -40c t a 125c for the 33910 and -40c t a 85c for the 34910, unless otherwise not ed. typical values noted reflect th e approximate parameter mean at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit spi interface timing ( figure 13 ) spi operating frequency f spiop ??4.0mhz sclk clock period t ps clk 250 ? n/a ns sclk clock high time (38) t w sclkh 110 ? n/a ns sclk clock low time (38) t w sclkl 110 ? n/a ns falling edge of cs to rising edge of sclk (38) t lead 100 ? n/a ns falling edge of sclk to cs rising edge (38) t lag 100 ? n/a ns mosi to falling edge of sclk (38) t sisu 40 ? n/a ns falling edge of sclk to mosi (38) t sih 40 ? n/a ns miso rise time (38) c l = 220pf t rso ? 40 ? ns miso fall time (38) c l = 220pf t fso ? 40 ? ns time from falling or rising edges of cs to: (38) - miso low-impedance - miso high-impedance t soen t sodis 0.0 0.0 ? ? 50 50 ns time from rising edge of sclk to miso data valid (38) 0.2 x v dd miso 0.8 x v dd , c l = 100pf t valid 0.0 ? 75 ns rst output pin reset low-level duration after v dd high (see figure 12 , page 19 ) t rst 0.65 1.0 1.35 ms reset deglitch filter time t rstdf 350 600 900 ns window watchdog configuration pin (wdconf) watchdog time period (39) external resistor r ext = 20k ? (1%) external resistor r ext = 200k ? (1%) without external resistor r ext (wdconf pin open) t pwd 8.5 79 110 10 94 150 11.5 108 205 ms notes 38. this parameter is guaranteed by pr ocess monitoring but, not production tested. 39. watchdog timing period ca lculation formula: t pwd [ms] = 0.466 * (r ext - 20) + 10 (r ext in k ?)
analog integrated circuit device data 14 freescale semiconductor 33910 electrical characteristics dynamic electrical characteristics l1 input wake-up filter time t wuf 8.0 20 38 s state machine timing delay between cs low-to-high transition (at end of spi stop command) and stop mode activation (40) t stop ? ? 5.0 s normal request mode timeout (see figure 12 , page 19 ) t nr tout 110 150 205 ms delay between spi command and hs turn on (41) 9v < v sup < 27v t s- on ? ? 10 s delay between spi command and hs turn off (41) 9v < v sup < 27v t s- off ? ? 10 s delay between normal request and normal mode after a watchdog trigger command (normal request mode) (40) t snr2n ? ? 10 s delay between cs wake-up ( cs low to high) in stop mode and: normal request mode, vdd on and rst high first accepted spi command t wucs t wuspi 9.0 90 15 ? 80 n/a s minimum time between rising and falling edge on the cs t 2 cs 4.0 ? ? s lin physical layer: driver characteristics for normal slew rate - 20.0kbit/sec (42) , (43) duty cycle 1: d1 = t bus_rec(min) /(2 x t bit ), t bit = 50s 7.0v v sup 18v d1 0.396 ? ? duty cycle 2: d2 = t bus_rec(max) /(2 x t bit ), t bit = 50s 7.6v v sup 18v d2 ? ? 0.581 lin physical layer: driver characteristics for slow slew rate - 10.4kbit/sec (42) , (44) duty cycle 3: d3 = t bus_rec(min) /(2 x t bit ), t bit = 96s 7.0v v sup 18v d3 0.417 ? ? s duty cycle 4: d4 = t bus_rec(max) /(2 x t bit ), t bit = 96s 7.6v v sup 18v d4 ? ? 0.590 s notes 40. this parameter is guaranteed by pr ocess monitoring but, not production tested. 41. delay between turn on or off command (rising edge on cs ) and hs on or off, excluding rise or fall time due to external load. 42. bus load r bus and c bus 1.0nf / 1.0k ? , 6.8nf / 660 ? , 10nf / 500 ? . measurement thresholds: 50% of tx d signal to lin signal threshold defined at each parameter. see figure 6 , page 17 . 43. see figure 7 , page 17 . 44. see figure 8 , page 17 . table 4. dynamic electrical characteristics (continued) characteristics noted under conditions 5.5v v sup 18v, -40c t a 125c for the 33910 and -40c t a 85c for the 34910, unless otherwise not ed. typical values noted reflect th e approximate parameter mean at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 15 33910 electrical characteristics dynamic electrical characteristics lin physical layer: driver characteristics for fast slew rate lin fast slew rate (programming mode) sr fast ?20?v / s lin physical layer: characteristics and wake-up timings (45) propagation delay and symmetry (46) propagation delay receiver, t rec_pd =max (t rec_pdr , t rec_pdf ) symmetry of receiver propagation delay t rec_pdf - t rec_pdr t rec_pd t rec_sym ? - 2.0 3.0 ? 6.0 2.0 s bus wake-up deglitcher (sleep and stop modes) (47) t propwl 42 70 95 s bus wake-up event reported from sleep mode (48) from stop mode (49) t wake t wake ? 9.0 ? 13 1500 17 s txd permanent dominant state delay t txddom 0.65 1.0 1.35 s pulse width modulation input pin (pwmin) pwmin pin (50) max. frequency to drive hs output pins f pwmin 10 khz notes 45. v sup from 7.0v to 18v, bus load r bus and c bus 1.0nf / 1.0k ? , 6.8nf / 660 ? , 10 nf / 500 ? . measurement thresholds: 50% of txd signal to lin signal threshold defined at each parameter. see figure 6 , page 17 . 46. see figure 9 , page 18 47. see figure 10 , page 18 for sleep and figure 11 , page 19 for stop mode. 48. the measurement is done with 1 f capacitor and 0ma current load on v dd . the value takes into account the delay to charge the capacitor. the delay is measured between the bus wake-up threshold (v buswu ) rising edge of the lin bus and when v dd reaches 3.0 v. see figure 10 , page 18 . the delay depends of the load and capacitor on v dd . 49. in stop mode, the delay is measured between the bus wake-up threshold (v buswu ) and the falling edge of the irq pin. see figure 11 , page 18 . 50. this parameter is guaranteed by pr ocess monitoring but, not production tested. table 4. dynamic electrical characteristics (continued) characteristics noted under conditions 5.5v v sup 18v, -40c t a 125c for the 33910 and -40c t a 85c for the 34910, unless otherwise not ed. typical values noted reflect th e approximate parameter mean at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 16 freescale semiconductor 33910 electrical characteristics timing diagrams timing diagrams figure 4. test circuit for transient test pulses (lin) figure 5. test circuit for transient test pulses (l1) figure 6. test circuit for lin timing measurements lin transient pulse pgnd generator 1.0nf ( note ) note: waveform per iso 7637-2. test pulses 1, 2, 3a, 3b. gnd 33910 lgnd agnd l1 transient pulse pgnd generator 1.0nf (note) 10k ? note: waveform per iso 7637-2. test pulses 1, 2, 3a, 3b. gnd 33910 lgnd agnd r0 and c0 combinations: ? 1.0k ? and 1.0nf ? 660 ? and 6.8nf ? 500 ? and 10nf v sup txd rxd lin r0 c0 c0
analog integrated circuit device data freescale semiconductor 17 33910 electrical characteristics timing diagrams figure 7. lin timing meas urements for normal slew rate figure 8. lin timing measurements for slow slew rate txd v lin_rec lin rxd t bit t bit t bus_dom (max) t bus_rec (min) t rec - max t dom - min t dom - min t rrec t rdom 28.4% v sup 58.1% v sup 40.0% v sup 60.0% v sup 74.4% v sup 42.2% v sup 40.0% v sup 58.1% v sup 28.4% v sup t bus_dom (min) t bus_rec (max) t dom - max t rec - min txd lin rxd t bit t bit t bus_dom (max) t bus_rec (min) t rec - max t dom - min t dom - min t rrec t rdom 25.1% v sup 61.6% v sup 40.0% v sup 60.0% v sup 77.8% v sup 38.9% v sup 40.0% v sup 61.6% v sup 25.1% v sup t bus_dom (min) t bus_rec (max) t dom - max t rec - min v lin_rec
analog integrated circuit device data 18 freescale semiconductor 33910 electrical characteristics timing diagrams figure 9. lin receiver timing figure 10. lin wake-up sleep mode timing v busrec v busdom v sup lin bus signal t rx_pdr t rx_pdf rxd v lin_rec dominant level 0.4 v sup v lin_rec lin vdd t prop wl t wake dominant level 0.4 v sup v lin_rec lin irq t prop wl t wake
analog integrated circuit device data freescale semiconductor 19 33910 electrical characteristics timing diagrams figure 11. lin wake-up stop mode timing figure 12. power on reset and normal request time-out timing figure 13. spi timing characteristics v sup v dd rst t rst t nrtout d0 d0 undefined don?t care d7 don?t care t lead t sih t sisu t lag t psclk t wsclkh t wsclkl t valid don?t care d7 t sodis cs sclk mosi miso t soen
analog integrated circuit device data 20 freescale semiconductor 33910 functional description introduction functional description introduction the 33910 is designed and developed as a highly integrated and cost-effective solution for automotive and industrial applications. for automotive body electronics, the 33910 is well suited to perform keypad applications via the lin bus. two power switches are provid ed on the device configured as high side outputs. other por ts are also provided, which include a wake-up capable pin amd a hall sensor port supply. an internal voltage regulator provides power to a mcu device. also included in this device is a lin physical layer, which communicates using a single wire. this enables this device to be compatible with 3-wire bus systems, where one wire is used for communication, one for battery, and one for ground. functional pin description see table 1, 33910 simplified application diagram , page 1 , for a graphic representation of the various pins referred to in the following paragraphs. also, see the pin diagram on page 3 for a description of the pin locations in the package. receiver output (rxd) the rxd pin is a digital output. it is the receiver output of the lin interface and reports the state of the bus voltage: rxd low when lin bus is dominant, rxd high when lin bus is recessive. transmitter input (txd) the txd pin is a digital input. it is the transmitter input of the lin interface and controls the state of the bus output (dominant when txd is low, recessive when txd is high). this pin has an internal pull-up to force recessive state in case the input is left floating. lin bus (lin) the lin pin represents the single-wire bus transmitter and receiver. it is suited for automotive bus systems and is compliant to the lin bus specification 2.0. the lin interface is only active during normal and normal request modes. serial data clock (sclk) the sclk pin is the spi clock input pin. miso data changes on the negative transi tion of the sclk. mosi is sampled on the positive edge of the sclk. master out slave in (mosi) the mosi digital pin receives spi data from the mcu. this data input is sampled on the positive edge of sclk. master in slave out (miso) the miso pin sends data to an spi-enabled mcu. it is a digital tri-state output used to shift serial data to the microcontroller. data on th is output pin changes on the negative edge of the sclk. when cs is high, this pin will remain in high-impedance state. chip select (cs ) cs is a active low digital input. it must remain low during a valid spi communication and allo w for several devices to be connected in the same spi bus without contention. a rising edge on cs signals the end of the transmission and the moment the data shifted in is latched. a valid transmission must consist of 8 bits only. while in stop mode a low-to-high level transition on this pin will generate a wake-up condition for the 33910. analog multiplexer (adout0) the adout0 pin can be configured via the spi to allow the mcu a/d converter to re ad the several inputs of the analog multiplexer, including the l1 input voltage and the internal junction temperature. pwm input control (pwmin) this digital input can control the high sides in normal request and normal mode. to enable pwm control, th e mcu must perform a write operation to the high side control register (hscr). this pin has an internal 20ua current pull-up. reset (rst ) this bidirectional pin is used to reset the mcu in case the 33910 detects a reset condition or to inform the 33910 that the mcu has just been reset. after release of the rst pin normal request mode is entered. the rst pin is an active low filtered input and output formed by a weak pull-up and a switchable pull-down structure which allows this pin to be shorted either to v dd or to gnd during software development without the risk of destroying the driver.
analog integrated circuit device data freescale semiconductor 21 33910 functional description functional pin description interrupt (irq ) the irq pin is a digital output used to signal events or faults to the mcu while in normal and normal request mode or to signal a wake-up from st op mode. this active low output will transition to high, only after the interrupt is acknowledged by a spi read of the respective status bits. watchdog configuration (wdconf) the wdconf pin is the configuration pin for the internal watchdog. a resistor can be connected to this pin to configure the window watchdog period. when connected directly to ground, the watchdog will be disabled. when this pin is left open, the watchdog period is fi xed to its lower precision internal default value (150ms typical). ground connection (agnd, pgnd, lgnd) the agnd, pgnd and lgnd pins are the analog and power ground pins. the agnd pin is the ground reference of the voltage regulator. the pgnd and lgnd pins are used for high current load return as in the lin interface pin. note: pgnd, agnd and lgnd pins must be connected together. digital/analog (l1) the l1 pin is a multi purpose input. it can be used as a digital input, which can be sampled by reading the spi and used for wake-up when 33910 is in low power mode or used as analog inputs for the analog multiplexer. when used to sense voltage outside the modu le, a 33kohm series resistor must be used on each input. when used as a wake-up input l1 can be configured to operate in cyclic-sense mode. in this mode, one of the high side switches is configured to be periodically turned on and sample the wake-up input. if a state change is detected between two cycles a wake-up is initiated. the 33910 can also wake-up from stop or sleep by a simple state change on l1. when used as analog input, the voltage present on the l1 pins is scaled down by an selectable internal voltage divider and can be routed to the adout0 output through the analog multiplexer. note: if l1 input is selected in the analog multiplexer, it will be disabled as digital input and remains disabled in low power mode. no wake-up feature is available in that condition. when the l1 input is not selected in the analog multiplexer, the voltage divide r is disconnected from that input. high side outputs (hs1 and hs2) these high side switches are able to drive loads such as relays or lamps. their structure is connected to the vs2 supply pin. the pins are s hort-circuit protected and also protected against overheating. hs1and hs2 are controlled by spi and can respond to a signal applied to the pwmin input pin. the hs1 and hs2 outputs can also be used during low power mode for the cyclic-sense of the wake input. power supply (vs1 and vs2) those are the battery level voltage supply pins. in an application, vs1 and vs2 pins must be protected against reverse battery connection and negative transient voltages, with external components. th ese pins sustain standard automotive voltage conditions such as load dump at 40v. the high side switches (hs1 and hs2) are supplied by the vs2 pin, all other internal blocks are supplied by vs1 pin. voltage sense pin (vsense) this input can be connected dire ctly to the battery line. it is protected against battery reverse conne ction. the voltage present in this input is scaled down by an internal voltage divider, and can be routed to the adout0 output pin and used by the mcu to read the battery voltage. the esd structure on this pin allows for excursion up to +40v and down to -27v, allowing this pin to be connected directly to the battery line. it is strongly recommended to connect a 10kohm resistor in series with this pin for protection purposes. hall sensor switchable supply pin (hvdd) this pin provides a switchable supply for external hall sensors. while in normal mode, this current limited output can be controlled through the spi. the hvdd pin needs to be connected to an external capacitor to stabilize the regulated output voltage. +5v main regulator output (vdd) an external capacitor has to be placed on the vdd pin to stabilize the regulated output voltage. the vdd pin is intended to supply a microcontro ller. the pin is current limited against shorts to gnd and over-temperature protected. during stop mode the voltage regulator does not operate with its full drive capabilities and the output current is limited. during sleep mode the regulator output is completely shut down.
analog integrated circuit device data 22 freescale semiconductor 33910 functional description functional internal block description functional internal block description figure 14. functional internal block diagram analog circuitry the 33910 is designed to operate under automotive operating conditions. a fully configurable window watchdog circuit will reset the connected mcu in case of an overflow. two low power modes are available with several different wake-up sources to reactivate the device. one analog / digital input can be sensed or used as the wake-up source. the device is capable of sensing the supply voltage (vsense) and the internal chip temperature (ctemp). high side drivers two current and temperature protected high side drivers with pwm capability are provided to drive small loads such as status led?s or small lamps. both drivers can be configured for periodic sense during low power modes. mcu interface the 33910 is providing its control and status information through a standard 8-bit spi inte rface. critical system events such as low- or high-voltage/temperature conditions as well as over-current conditions in any of the driver stages can be reported to the connected mcu via irq or rst. the high side driver outputs can be cont rolled via the spi register as well as the pwmin input. the integrated lin physical layer interface can be configured via spi register and its communication is driven through the rxd and txd device pins. all internal analog sources are multiplexed to the adout0 pin. voltage regulator outputs two independent voltage regu lators are implemented on the 33910. the vdd main regulator output is designed to supply a mcu with a precise 5v. the switchable hvdd output is dedicated to supply small peripherals as hall sensors. lin physical layer interface the 33910 provides a lin 2.0 compatible lin physical layer interface with select able slew rate and various diagnostic features. mc33910 - functional block diagram a na l og circuitr y mcu inter f ace and out p ut control driver s a nalog c ircuitr y mcu interface and out p ut contro l s pi int e rf ace h i g h s ide drivers h s 1 - h s 2 l in physical layer interface digital / analog input voltage & temperature sense wake-up integrated supply hall sensor supply hvdd window watchdog voltage regulator vdd i ntegrated suppl y l in interface / control reset & ir q logic hs - pwm c ontrol a nalo g output 0
analog integrated circuit device data freescale semiconductor 23 33910 functional device operations operational modes functional device operations operational modes introduction the 33910 offers three main operating modes: normal (run), stop, and sleep (low power). in normal mode the device is active and is operating under normal application conditions. the stop and sleep modes are low power modes with wake-up capabilities. in stop mode the voltage regulator still supplies the mcu with v dd (limited current capability) and in sleep mode the voltage regulator is turned off (v dd = 0 v). wake-up from stop mode is initiated by a wake-up interrupt. wake-up from sleep mode is done by a reset and the voltage regulator is turned back on. the selection of the different modes is controlled by the mod1:2 bits in the mode control register (mcr). figure 15 describes how transitions are done between the different operating modes and table 5 , 25 , gives an overview of the operating mode. reset mode the 33910 enters the reset mode after a power up. in this mode, the rst pin is low for 1ms (typical value). after this delay, the 33910 enters the normal request mode and the rst pin is driven high. the reset mode is entered if a reset condition occurs (v dd low, watchdog trigger fail, after a wake-up from sleep mode, normal request mode time-out occurs). normal request mode this is a temporary mode automatically accessed by the device after the reset mode or after a wake-up from stop mode. in normal request mode, the vdd regulator is on, the reset pin is high and the lin is operating in rx only mode. as soon as the device enters the normal request mode an internal timer is started for 150ms (typical value). during these 150ms, the mcu must configure the timing control register (timcr) and the mcr with mod2 and mod1 bits ste = 0 to enter in normal mode. if within the 150ms timeout the mcu does not command the 33910 to normal mode, it will enter in reset mode. if the wdconf pin is grounded in order to disable the watchdog function, the 33910 goes directly in normal mode after the reset mode. if the wdconf pin is open, the 33910 stays typically for 150ms in normal request before entering in normal mode. normal mode in normal mode, all 33910 functions are active and can be controlled by the spi and the pwmin pin. the vdd regulator is on and delivers its full current capability. if an external resistor is connected between the wdconf pin and the ground, the window watchdog function will be enabled. the wake-up input (l1) can be read as a digital input or have its voltage routed through the analog-multiplexer. the lin interface has slew rate and timing compatible with the lin protocol specification 2.0. the lin bus can transmit and receive information. the high side switches are active and have pwm capability according to the spi configuration. the interrupts are generated to report failures 5 for v sup over/under-voltage, thermal shutdown or thermal shutdown prewarning on the main regulator. sleep mode the sleep mode is a low power mode. from normal mode, the device enters the sl eep mode by sending one spi command through the mcr. all blocks are in their lowest power consumption condition. only some wake-up sources (wake-up input with or without cyclic sense, forced wake-up and lin receiver) are active. the 5v regulator is off. the internal low-power oscillator may be active if the ic is configured for cyclic-sense. in th is condition, one of the high side switches is turned on periodically and the wake-up inputs are sampled. wake-up from sleep mode is similar to a power-up. the device goes in reset mode exce pt that the spi will report the wake-up source and the batfail flag is not set. stop mode the stop mode is the second low power mode, but in this case the 5v regulator is on with limited current drive capability. the application mcu is always supplied while the 33910 is operating in stop mode. the device can enter in stop mode only by sending the spi command. when the application is in this mode, it can wake-up from the 33910 side (f or example: cyclic sense, force wake-up, lin bus, wake inputs) or the mcu side (cs , rst pins). wake-up from stop mode will transition the 33910 to normal request mode and generates an interrupt except if the wake-up event is a low to high transition on the cs pin or comes from the rst pin.
analog integrated circuit device data 24 freescale semiconductor 33910 functional device operations operational modes figure 15. operating modes and transitions normal request timeout expired (t nrtout ) v dd high and reset delay (t rst ) expired v dd low v dd low wd failed v dd low (>t nrtout ) expired and vsuv = 0 sleep command stop command wake-up (reset) wd trigger wd disabled power up wake-up (interrupt) legend wd: watchdog wd disabled: watchdog disabled (w dconf pin connected to gnd) wd trigger: watchdog is triggered by spi command wd failed: no watchdog trigger or trigger occurs in closed window stop command: stop command sent via the spi sleep command: sleep command sent via the spi wake-up from stop mode: l1 state change, lin bus wake-up, periodic wake-up, cs rising edge wake-up or rst wake-up. v dd low wake-up from sleep mode: l1 state change, lin bus wake-up, periodic wake-up. power down normal request reset normal sleep stop
analog integrated circuit device data freescale semiconductor 25 33910 functional device operations operational modes interrupts interrupts are used to signal a microcontroller that a peripheral needs to be serviced. the interrupts which can be generated change according to the operating mode. while in normal and normal request modes the 33910 signals through interrupts special conditions which may require a mcu software action. interr upts are not generated until all pending wake-up sources are read in the interrupt source register (isr). while in stop mode, interrupts are used to signal wake-up events. sleep mode does not use interrupts, wake-up is performed by powering-up the mcu. in normal and normal request mode the wake-up source can be read by spi. the interrupts are signaled to the mcu by a low logic level of the irq pin, which will remain low until the interrupt is acknowledged by a spi read. the irq pin will then be driven high. interrupts are only asserted while in normal-, normal request and stop mode. interrupts are not generated while the rst pin is low. following is a list of the interrupt sources in normal and normal request modes, some of those can be masked by writing to the spi-interru pt mask register (imr). low voltage interrupt signals when the supply line (vs1) voltage drops below the vsuv threshold ( v suv ). high voltage interrupt signals when the supply line (vs1) voltage increases above the vsov threshold ( v sov ). over-temperature prewarning signals when the 33910 temp erature has reached the pre- shutdown warning threshold. it is used to warn the mcu that an over-temperature shutdown in the main 5v regulator is imminent. lin over-current shutdown / over-temperature shutdown / txd stuck at dominant / rxd short-circuit these signal faulty conditions in the lin interface (except the lin over-current) that had le d to disable the lin driver. in order to restart operation, the fault must be removed and must be acknowledged by reading the spi. the linoc bit functionality in the lin status register (linsr) is to indicate that an lin over-current occurred and the driver stays enabled. high side over-temperature shutdown signals a shutdown of the high side outputs. reset to reset an mcu, the 33910 drives the rst pin low for the time the reset condition lasts. after the reset source has been removed the state machine will drive the rst output low for at least 1ms typical value before driving it high. in the 33910 four main reset sources exist: 5v regulator low-voltage-reset (v rst th ) the 5v regulator output v dd is continuously monitored against brown outs. if the supply monitor detects that the voltage at the vdd pin has dropped below the reset threshold v rst th the 33910 will issue a reset. in case of over- table 5. operating modes overview function reset mode normal request mode normal mode stop mode sleep mode vdd full full full stop - hvdd - spi (51) spi - - hsx - spi/pwm (52) spi/pwm note (53) note (54) analog mux - spi spi - - l1 - input input wake-up wake-up lin - rx-only full/rx-only rx-only/wake-up wake-up watchdog - 150ms (typ.) timeout on (55) /off - - vsense on on on vdd - notes 51. operation can be enabled/controlled by the spi. 52. operation can be controlled by the pwmin input. 53. hsx switches can be configured for cyclic sense operation in stop mode. 54. hsx switches can be configured fo r cyclic sense operation in sleep mode. 55. windowing operation when enabled by an external resistor.
analog integrated circuit device data 26 freescale semiconductor 33910 functional device operations operational modes temperature, the voltage regulator will be disabled and the voltage monitoring will issue a vddot flag independently of the v dd voltage. window watchdog overflow if the watchdog counter is not properly serviced while its window is open, the 33910 will detect a mcu software runaway and will reset the microcontroller. wake-up from sleep mode during sleep mode, the 5v regulator is not active, hence all wake-up requests from sleep mode require a power-up/ reset sequence. external reset the 33910 has a bidirectional reset pin which drives the device to a safe state (same as reset mode) for as long as this pin is held low. the r st pin must be held low long enough to pass the internal glitch filter and get recognized by the internal reset circuit. this functionality is also active in stop mode. after the rst pin is released, there is no extra t rst to be considered. wake-up capabilities once entered in to one of the low-power modes (sleep or stop) only wake-up sources can bring the device into normal mode operation. in stop mode, a wake-up is signaled to the mcu as an interrupt, while in sleep mode the wake-up is performed by activating the 5v regulator and resetting the mcu. in both cases the mcu can detect the wake-up source by accessing the spi registers. there is no spec ific spi register bit to signal a cs wake-up or external reset. if necessary this condition is detected by excluding all other possible wake-up sources. wake-up from wake-up input (l1) with cyclic sense disabled the wake-up line is dedicated to sense state changes of external switches and wake-up the mcu (in sleep or stop mode). in order to select and activate direct wake-up from the l1 input, the wake-up control register (wucr) must be configured with l1we input enabled. the wake-up input state is read through the wake -up status register (wusr). l1 input is also used to perform cyclic-sense wake-up. note: selecting the l1 input in the analog multiplexer before entering low power mode will disable the wake-up capability of the l1 input. wake-up from wake-up input (l1) with cyclic sense timer enabled the sbclin can wake-up at the end of a cyclic sense period if on the wake-up input lines (l1) a state change occurs. the hsx switch is activated in sleep or stop modes from an internal timer. cyclic sense and force wake-up are exclusive. if cyclic sense is enabled, the force wake-up can not be enabled. in order to select and activate the cyclic sense wake-up from the l1 input, before entering in low power modes (stop or sleep modes), the following spi set-up has to be performed: ? in wucr: select the l1 input to wu-enable. ? in hscr: enable hsx. ? in timcr: select the cs/ wd bit and determine the cyclic sense period with cystx bits. ? perform goto sleep/stop command. forced wake-up the 33910 can wake-up automatically after a predetermined time spent in sleep or stop mode. cyclic sense and forced wake-up are exclusive. if forced wake-up is enabled, the cyclic sense can not be enabled. to determine the wake-up peri od, the following spi set-up has to be sent before entering in low power modes: ? in timcr: select the cs/ wd bit and determine the low power mode period with cystx bits. ? in hscr: the hsx bit must be disabled. cs wake-up while in stop mode, a rising edge on the cs will cause a wake-up. the c s wake-up does not generate an interrupt and is not reported on spi. lin wake-up while in the low power modes the 33910 monitors the activity on the lin bus. a dominant pulse larger than t propwl followed by a dominant to recessive transition will cause a lin wake-up. this behavior prot ects the system from a short- to-ground bus condition. rst wake-up while in stop mode, the 33910 can wake-up when the rst pin is held low long enough to pass the internal glitch filter. then, the 33910 will ch ange to normal request or normal modes depending on the wdconf pin configuration. the r st wake-up does not generate an interrupt and is not reported via spi. from stop mode, the following wake-up events can be configured: ? wake-up from l1 input without cyclic sense ? cyclic sense wake-up inputs ? force wake-up ? cs wake-up ? lin wake-up ? rst wake-up from sleep mode, the following wake-up events can be configured: ? wake-up from l1 input without cyclic sense
analog integrated circuit device data freescale semiconductor 27 33910 functional device operations operational modes ? cyclic sense wake-up inputs ? force wake-up ? lin wake-up window watchdog the 33910 includes a configurable window watchdog which is active in normal mode. the watchdog can be configured by an external resistor connected to the wdconf pin. the resistor is used to achieve higher precision in the timebase used for the watchdog. spi clears are performed by writing through the spi in the mod bits of the mcr. during the first half of the spi timeout watchdog clears are not allowed; but after the first half of the pspi -timeout window the clear operation opens. if a clear operation is performed outside the window, the 33910 will reset the mcu, in the same way as when the watchdog overflows. figure 16. window watchdog operation to disable the watchdog function in normal mode the user must connect the wdconf pin to ground. this measure effectively disables normal request mode. the wdoff bit in the wdsr will be set. this condition is only detected during reset mode. if neither a resistor nor a co nnection to ground is detected, the watchdog falls back to the internal lower precision timebase of 150ms (typ.) and signals the faulty condition through the wdsr. the watchdog timebase can be further divided by a prescaler which can be configured by the timcr. during normal request mode, the window watchdog is not active but there is a 150ms (typ.) timeout for leaving the normal request mode. in case of a timeout, the 33910 will enter into reset mode, resetting the micr ocontroller before entering again into normal request mode. high side output pins hs1 and hs2 these outputs are two high side drivers intended to drive small resistive loads or leds incorporating the following features: ? pwm capability (software maskable) ? open load detection ? current limitation ? over-temperature shutdown (with maskable interrupt) ? high-voltage shutdown (software maskable) ? cyclic sense the high side switches are controlled by the bits hs1:2 in the high side control register (hscr). pwm capability (direct access) each high side driver offers additional (to the spi control) direct control via the pwmin pin. if both the bits hs1 and pwmhs1 are set in the high side control register (hscr), then the hs1 driver is turned on if the pwmin pin is high and turned of if the pwmin pin is low. this applies to hs2 configuring hs2 and pwmhs2 bits. wd period (t pwd ) window closed no watchdog clear allowed window open for watchdog clear wd timing x 50% wd timing x 50% wd timing selected by register on wdconf pin
analog integrated circuit device data 28 freescale semiconductor 33910 functional device operations operational modes figure 17. high side drivers hs1 and hs2 open load detection each high side driver signals an open load condition if the current through the high side is below the open load current threshold. the open load condition is indi cated with the bits hs1op and hs2op in the high side status register (hssr). current limitation each high side driver has an output current limitation. in combination with the over-tem perature shutdown the high- side drivers are protected against over-current and short- circuit failures. when the driver operates in th e current limitation area, it is indicated with the bits hs1cl and hs2cl in the hssr. note: if the driver is operatin g in current limitation mode, excessive power might be dissipated. over-temperature protection (hs interrupt) both high side drivers are protected against over- temperature. in case of an ov er-temperature condition both high side drivers are shut down and the event is latched in the interrupt control module. the shutdown is indicated as hs interrupt in the interrupt source register (isr). a thermal shutdown of the high side drivers is indicated by setting all hsxop and hsxcl bits simultaneously. if the bit hsm is set in the interrupt mask r egister (imr), then an interrupt (irq ) is generated. a write to the high side control register (hscr), when the over-temperature conditio n is gone, will re-enable the high side drivers. high-voltage shutdown in case of a high voltage condition and if the high voltage shutdown is enabled (bit hvse in the mode control register (mcr) is set) both high si de drivers are shut down. a write to the high side control register (hscr), when the high voltage condition is go ne, will re-enable the high side drivers. sleep and stop mode the high side driver can be enabled to operate in sleep and stop mode for cyclic sensing. also see table 5, operating modes overview . high side - driver charge pump open load detection current limitation overtemperture shutdown (interrupt maskable) high voltage shutdown (maskable) control on/off status pwmin v dd pwmhsx hsx hvse hsxop hsxcl mod1:2 interrupt control module hsx vs2 high voltage shutdown high-side interrupt v dd wakeup module cyclic sense
analog integrated circuit device data freescale semiconductor 29 33910 functional device operations operational modes lin physical layer the lin bus pin provides a physical layer for single-wire communication in automotive applications. the lin physical layer is designed to meet the lin physical layer specification and has the following features: ? lin physical la yer 2.0 compliant ? slew rate selection ? over-current shutdown ? over-temperature shutdown ? lin pull-up disable in stop and sleep modes ? advanced diagnostics ? lin dominant voltage level selection the lin driver is a low side mosfet with over-current and thermal shutdown. an internal pull-up resistor with a serial diode structure is integrated, so no external pull-up components are required for the application in a slave mode. the fall time from dominant to recessive and the rise time from recessive to dominant is controlled. the symmetry between both slopes is guaranteed. lin pin the lin pin offers a high susceptibility immunity level from external disturbance, gu aranteeing communication. figure 18. lin interface slew rate selection the slew rate can be selected for optimized operation at 10.4 and 20kbit/s as well as a fast baud rate for test and programming. the slew rate can be adapted with the bits lsr1:0 in the lin control regi ster (lincr). the initial slew rate is optimized for 20kbit/s. lin pull-up disable in stop and sleep mode to improve performance and for safe behavior in case of lin bus short to ground or lin bus leakage during low power mode the internal pull-up resi stor on the lin pin can be disconnected by clearing the linpe bit in the mcr. the bit linpe also changes the bus wake-up threshold ( v buswu ). in case of a lin bus short to gnd, this feature will reduce the current consumption in stop and sleep modes. over-current shutdown (lin interrupt) the output low side fet is protected against over-current conditions. in case of an over-current condition (e.g. lin bus high-voltage high side rxonly mod1:2 lsr0:1 linpe ldvs interrupt control module lin ? driver slope and slew rate control over-current shutdown (interrupt maskable) over-temperature shutdown (interrupt maskable) vs1 wake-up rxshort linoc txdom linot lin filter slope control 30k lgnd lin receiver txd rxd interrupt shutdown wake-up wake-up module
analog integrated circuit device data 30 freescale semiconductor 33910 functional device operations operational modes short to v bat ), the transmitter will not be shut down. the bit linoc in the lin status register (linsr) is set. if the bit linm is set in the interrupt mask register (imr) an interrupt irq will be generated. over-temperature shut down (lin interrupt) the output low side fet is protected against over- temperature conditions. in ca se of an over-temperature condition, the transmitter will be shut down and the bit linot in the lin status register (linsr) is set. if the bit linm is set in the interrupt mask register (imr) an interrupt irq will be generated. the transmitter is automatically re-enabled once the condition is gone and txd is high. a read of the lin status regi ster (linsr) with the txd pin will re-enable the transmitter. rxd short circuit detection (lin interrupt) the lin transceiver has a short-circuit detection for the rxd output pin. in case of an s hort-circuit condition, either 5v or ground, the bit rxshort in the lin status register (linsr) is set and the transmitter is shutdown. if the bit linm is set in the interrupt mask register (imr) an interrupt irq will be generated. the transmitter is automatically re-enabled once the condition is gone (transition on rxd) and txd is high. a read of the lin status regi ster (linsr) without the rxd pin short circuit condition will clear the bit rxshort. txd dominant detection (lin interrupt) the lin transceiver monitors the txd input pin to detect stuck in dominant (0v) condition. in case of a stuck condition (txd pin 0v for more than 1 se cond (typ.)) the transmitter is shut down and the bit txdom in the lin status register (linsr) is set. if the bit linm is set in the interrupt mask register (imr) an interrupt irq will be generated. the transmitter is automatical ly re-enabled once txd is high. a read of the lin status register (linsr) with the txd pin is high will clear the bit txdom. lin dominant voltage level selection the lin dominant voltage leve l can be selected by the bit ldvs in the lin contro l register (lincr). lin receiver operation only while in normal mode the activation of the rxonly bit disables the lin tx driver. in th e case of a lin error condition this bit is automatically set. in case a low power mode is selected with this bit set, t he lin wake-up functionality is disabled, then, in stop mode, t he rxd pin will reflect the state of the lin bus. stop mode and wake-up feature during stop mode operation the transmitter of the physical layer is disabled. in case the bit lin-pu was set in the stop mode sequence the internal pull-up resistor is disconnected from vsup and a small current source keeps the lin pin in the recessive state. the receiver is still active and able to detect wake-up events on the lin bus line. a dominant level longer than t propwl followed by a rising edge will generate a wake-up interrupt and will be reported in the isr. also see figure 11 , page 19 . sleep mode and wake-up feature during sleep mode operation the transmitter of the physical layer is disabled. in case the bit lin-pu was set in the sleep mode sequence the internal pull-up resistor is disconnected from v sup and a small current source keeps the lin pin in recessive state. t he receiver is still active to be able to detect wake-up events on the lin bus line. a dominant level longer than t propwl followed by a rising edge will generate a system wake-up (reset) and will be reported in the isr. also see figure 10 , page 18 .
analog integrated circuit device data freescale semiconductor 31 33910 functional device operations logic commands and registers logic commands and registers spi and configuration the spi creates the communication link between a microcontroller (master) and the 33910. the interface consists of four pins (see figure 19 ): ? cs ? chip select ?mosi ? master-out slave-in ?miso ? master-in slave-out ?sclk? serial clock a complete data transfer via the spi consists of 1 byte. the master sends 4 bits of addre ss (a3:a0) + 4 bits of control information (c3:c0) and the slave replies with 3 system status bits and one not defined bit (vms,lins,hss,n.d.) + 4 bits of status information (s3:s0). figure 19. spi protocol during the inactive phase of the cs (high), the new data transfer is prepared. the falling edge of the cs indicates the start of a new data transfer and puts the miso in the low-impedance state and latches the analog status da ta (register read data). with the rising edge of the spi clock (sclk), the data is moved to miso/mosi pins. with the falling edge of the spi clock (sclk) the data is sampled by the receiver. the data transfer is only valid if exactly 8 sample clock edges are present during the active (low) phase of cs . the rising edge of the chip select cs indicates the end of the transfer and latches t he write data (mosi) into the register. the cs high forces miso to the high-impedance state. register reset values are described along with the reset condition. reset condition is the condition causing the bit to be set to its reset value. th e main reset conditions are: - power-on reset (por): level at which the logic is reset and batfail flag sets. - reset mode - reset done by the rst pin (ext_reset) cs mosi miso sclk a2 a1 a0 c3 c2 c1 c0 a3 vms lins hss ? s3 s2 s1 s0 read data latch rising edge of sclk change miso/miso output falling edge of sclk sample miso/miso input write data latch register write data register read data
analog integrated circuit device data 32 freescale semiconductor 33910 functional device operations logic commands and registers spi register overview . table 7 summarizes the spi register content for control info rmation (c3:c0)=w and status information (s3:s0) = r. note: address $8 and $9 are reserved and must not be used. table 6. system status register adress(a3:a0) register name / read / write information bit 7654 $0 - $f syssr - system status register r vms lins hss - table 7. spi register overview adress(a3:a0) register name / read / write information bit 3210 $0 mcr - mode control register w hvse linpe mod2 mod1 vsr - voltage status register r vsov vsuv vddot batfail $1 vsr - voltage status register r vsov vsuv vddot batfail $2 wucr - wake-up control register w - - - l1we wusr - wake-up status register r - - - l1 $3 wusr - wake-up status register r - - - l1 $4 lincr - lin control register w ldvs rxonly lsr1 lsr0 linsr - lin status register r rxshort txdom linot linoc $5 linsr - lin status register r rxshort txdom linot linoc $6 hscr - high side control register w pwmhs2 pwmhs1 hs2 hs1 hssr - high side status register r hs2op hs2cl hs1op hs1cl $7 hssr - high side status register r hs2op hs2cl hs1op hs1cl $a timcr - timing control register w cs/wd wd2 wd1 wd0 cyst2 cyst1 cyst0 wdsr - watchdog status register r wdto wderr wdoff wdwo $b wdsr - watchdog status register r wdto wderr wdoff wdwo $c amuxcr - analog multiplexer control register w l1ds mx2 mx1 mx0 $d cfr - configuration register w hvdd cysx8 - - $e imr - interrupt mask register w hsm - linm vmm isr - interrupt source register r isr3 isr2 isr1 isr0 $f isr - interrupt source register r isr3 isr2 isr1 isr0
analog integrated circuit device data freescale semiconductor 33 33910 functional device operations logic commands and registers register definitions system status register - syssr the system status register (syssr) is always transferred with every spi transmission and gives a quick system status overview. it summarizes the st atus of the voltage status register (vsr), lin status register (linsr) and the hssr. vms - voltage monitor status this read-only bit indicates that one or more bits in the voltage status register (vsr) are set. 1 = voltage monitor bit set 0 = none figure 20. voltage monitor status lins - lin status this read-only bit indicates that one or more bits in the lin status register (linsr) are set. 1 = lin status bit set 0 = none figure 21. lin status hss - high side switch status this read-only bit indicates that one or more bits in the hssr are set. 1 = high side status bit set 0 = none figure 22. high side status mode control register - mcr the mcr allows to switch between the operation modes and to configure the 33910. wr iting the mcr will return the voltage status register (vsr). hvse - high-voltage shutdown enable this write-only bit enables/dis ables automatic shutdown of the high side and the low side drivers during a high-voltage vsov condition. 1 = automatic shutdown enabled 0 = automatic shutdown disabled linpe - lin pull-up enable. this write-only bit enables/disables the 30k ? lin pull-up resistor in stop and sleep modes. this bit also controls the lin bus wake-up threshold. 1 = lin pull-up resistor enabled 0 = lin pull-up resistor disabled table 8. system status register s7 s6 s5 s4 read vms lins hss ?. vms batfail vddot vsuv vsov lins linoc linot txdom rxshort table 9. mode control register - $0 c3 c2 c1 c0 write hvse linpe mod2 mod1 reset value 11-- reset condition por por - - hs2op hs2cl hs1op hs1cl hss
analog integrated circuit device data 34 freescale semiconductor 33910 functional device operations logic commands and registers mod2, mod1 - mo de control bits these write-only bits select the operating mode and allow to clear the watchdog in accordance with table 11 mode control bits. table 10. mode control bits voltage status register - vsr returns the status of the several voltage monitors. this register is also returned when writing to the mcr. vsov - v sup over-voltage this read-only bit indicates an over-voltage condition on the vs1 pin. 1 = over-voltage condition. 0 = normal condition. vsuv - v sup under-voltage this read-only bit indicates an under-voltage condition on the vs1 pin. 1 = under-voltage condition. 0 = normal condition. vddot - main voltage re gulator over-temperature warning this read-only bit indicates that the main voltage regulator temperature reached the ov er-temperature prewarning threshold. 1 = over-temperature prewarning 0 = normal batfail - battery fail flag. this read-only bit is set during power-up and indicates that the 33910 had a power on reset (por). any access to the mcr or vo ltage status register (vsr) will clear the batfail flag. 1 = por reset has occurred 0 = por reset has not occurred wake-up control register - wucr this register is used to control the digital wake-up input. writing the wake-up control register (wucr) will return the wake-up status register (wusr). table 12. wake-up control register - $2 l1we - wake-up input enable this write-only bit enables/disables the l1 input. in stop and sleep mode the l1we bit activates the l1 input for wake- up. if the l1 input is selected on the analog multiplexer, the l1we is masked to 0. 1 = wake-up input enabled. 0 = wake-up input disabled. wake-up status register - wusr this register is used to monitor the digital wake-up inputs and is also returned when writing to the wake-up control register (wucr). l1 - wake-up input this read-only bit indicates the st atus of the l1 input. if the l1 input is not enabled then the wake-up status will return 0. after a wake-up form stop or sleep mode this bit also allows to verify the l1 input has caused the wake-up, by first reading the interrupt status re gister (isr) and then reading the wake-up status register (wusr). 1 = l1 wake-up. 0 = l1 wake-up disabled or selected as analog input. mod2 mod1 description 0 0 normal mode 0 1 stop mode 1 0 sleep mode 1 1 normal mode + watchdog clear table 11. voltage st atus register - $0/$1 s3 s2 s1 s0 read vsov vsuv vddot batfail c3 c2 c1 c0 write 0 0 0 l1we reset value 1111 reset condition por, reset mode or ext_reset table 13. wake-up status register - $2/$3 s3 s2 s1 s0 read---l1
analog integrated circuit device data freescale semiconductor 35 33910 functional device operations logic commands and registers lin control register - lincr this register controls the lin physical interface block. writing the lin control register (lincr) returns the lin status register (linsr). * lin failure gone: if lin failure (overtemp, txd/rxd short) was set, the flag resets automatically when the failure is gone. ldvs - lin dominant voltage select this write-only bit controls the lin dominant voltage: 1 = lin dominant voltage = v lin_dom_1 (1.7v typ) 0 = lin dominant voltage = v lin_dom_0 (1.1v typ) rxonly - lin receiver operation only this write-only bit controls the behavior of the lin transmitter. in normal mode the activation of the rxonly bit disables the lin transmitter. in case of a lin error condition this bit is automatically set. in stop mode this bit disables the lin wake-up functionality and the rxd pin will reflect the state of the lin bus. 1 = only lin receiver active (normal mode) or lin wake- up disabled (stop mode). 0 = lin fully enabled. lsrx - lin slew-rate this write-only bit controls the lin driver slew-rate in accordance with table 15 . table 15. lin slew-rate control lin status register - linsr this register returns the status of the lin physical interface block and is also returned when writing to the lin control register (lincr). rxshort - rxd pin short circuit this read-only bit indicates a short-circuit condition on the rxd pin (shorted either to 5.0v or to ground). the short circuit delay must be 8s worst case to be detected and to shutdown the driver. to clear this bit, it must be read after the condition is gone (transition detected on rxd pin). the lin driver is automatically re-e nabled once the condition is gone. 1 = rxd short circuit condition. 0 = none. txdom - txd permanent dominant this read-only bit signals the detection of a txd pin stuck at dominant (ground) condition and the resultant shutdown in the lin transmitter. this cond ition is detected after the txd pin remains in dominant state for more than 1 second typical value. to clear this bit, it must be read after txd has gone high. the lin driver is automatically re-enabled once txd goes high. 1 = txd stuck at dominant fault detected. 0 = none. linot - lin driver o ver-temperature shutdown this read-only bit signals that the lin transceiver was shutdown due to over-temperature. the transmitter is automatically re-enabled after the over-temperature condition is gone and txd is high. the linot bit is cleared after spi read once the condition is gone. 1 = lin over-temperature shutdown 0 = none linoc - lin driver over-current shutdown this read-only bit signals an over-current condition occurred on the lin pin. the li n driver is not shutdown but an irq is generated. to clear this bi t, it must be read after the condition is gone. 1 = lin over-current shutdown 0 = none table 14. lin control register - $4 c3 c2 c1 c0 write ldvs rxonly lsr1 lsr0 reset value 0000 reset condition por, reset mode or ext_reset por, reset mode, ext_reset or lin failure gone* por lsr1 lsr0 description 0 0 normal slew rate (up to 20kb/s) 0 1 slow slew rate (up to 10kb/s) 1 0 fast slew rate (up to 100kb/s) 1 1 reserved table 16. lin status register - $4/$5 s3 s2 s1 s0 read rxshort txdom linot linoc
analog integrated circuit device data 36 freescale semiconductor 33910 functional device operations logic commands and registers high side control register - hscr this register controls the opera tion of the high side drivers. writing to this register return s the high side status register (hssr). pwmhsx - pwm input control enable this write-only bit enables/disables the pwmin input pin to control the high side switch. the high side switch must be enabled (hsx bit). 1 = pwmin input controls hs1 output. 0 = hsx is controlled only by spi. hsx - high side switch control. this write-only bit enables/disables the high side switch. 1 = hsx switch on. 0 = hsx switch off. high side status register - hssr this register returns the status of the high side switch and is also returned when writing to the hscr. high side thermal shutdown a thermal shutdown of the high side drivers is indicated by setting the hsxop and hsxcl bits simultaneously. hsxop - high side switch open-load detection this read-only bit signals that the high side switch is conducting current below a certain threshold indicating possible load disconnection. 1 = hsx open load detected (or thermal shutdown) 0 = normal hsxcl - high side current limitation this read-only bit indicates t hat the high side switch is operating in current limitation mode. 1 = hsx in current limitat ion (or thermal shutdown) 0 = normal timing control register - timcr this register is a double purpo se register which allows to configure the watchdog and the cyclic sense periods. writing to the timcr will also return the wdsr. cs/wd - cyclic sense or watchdog prescaler select. this write-only bit selects wh ich prescaler is being written to, the cyclic sense prescaler or the watchdog prescaler. 1 = cyclic sense prescaler selected 0 = watchdog prescaler select wdx - watchdog prescaler this write-only bits selects the divider for the watchdog prescaler and therefore sele cts the watchdog period in accordance with table 20 . this configuration is valid only if windowing watchdog is active. table 20. watchdog prescaler table 17. high side control register - $6 c3 c2 c1 c0 write pwmhs2 pwmhs1 hs2 hs1 reset value 00 0 0 reset condition por por, reset mode, ext_reset, hsx over-temp or (vsov & hvse) table 18. high side status register - $6/$7 s3 s2 s1 s0 read hs2op hs2cl hs1op hs1cl table 19. timing control register - $a c3 c2 c1 c0 write cs/wd wd2 wd1 wd0 cyst2 cyst1 cyst0 reset value - 000 reset condition -por wd2 wd1 wd0 prescaler divider 0 0 0 1 0 0 1 2 0 1 0 4 0 1 1 6 1 0 0 8 1 0 1 10 1 1 0 12 1 1 1 14
analog integrated circuit device data freescale semiconductor 37 33910 functional device operations logic commands and registers cystx - cyclic sense period prescaler select this write-only bits selects the interval for the wake-up cyclic sensing together with the bit cysx8 in the configuration register (cfr) (see page 38 ). this option is only active if the high side switch is enabled when entering in stop or sleep mode. otherwise a timed wake-up is performed after the period shown in table 21 . table 21. cyclic sense interval watchdog status register this register returns the watc hdog status information and is also returned when writing to the timcr. wdto - watchdog time out this read-only bit signals the last reset was caused by either a watchdog timeout or by an attempt to clear the watchdog within the window closed. any access to this register or the timcr will clear the wdto bit. 1 = last reset caused by watchdog timeout 0 = none wderr - watchdog error this read-only bit signals the detection of a missing watchdog resistor. in this condition the watchdog is using the internal, lower precision timebase. the windowing function is disabled. 1 = wdconf pin resistor missing 0 = wdconf pin resistor not floating wdoff - watchdog off this read-only bit signals th at the watchdog pin connected to gnd and therefore disabled. in this case watchdog timeouts are disabled and the device automatically enters normal mode out of reset. th is might be necessary for software debugging and for programming the flash memory. 1 = watchdog is disabled 0 = watchdog is enabled wdwo - watchdog window open this read-only bit signals when the watchdog window is open for clears. the purpose of this bit is for testing. should be ignored in case wderr is high. 1 = watchdog window open 0 = watchdog window closed analog multiplexer control register - muxcr this register controls the analog multiplexer and selects the divider ration for the l1 input divider. l1ds - l1 analog input divider select this write-only bit selects the resistor divider for the l1 analog input. voltage is internally clamped to vdd. 0 = l1 analog divider: 1 1 = l1 analog divider: 3.6 (typ.) cysx8 (56) cyst2 cyst1 cyst0 interval x 0 0 0 no cyclic sense 0 0 0 1 20ms 0 0 1 0 40ms 0 0 1 1 60ms 0 1 0 0 80ms 0 1 0 1 100ms 0 1 1 0 120ms 0 1 1 1 140ms 1 0 0 1 160ms 1 0 1 0 320ms 1 0 1 1 480ms 1 1 0 0 640ms 1 1 0 1 800ms 1 1 1 0 960ms 1 1 1 1 1120ms notes 56. bit cysx8 is located in configuration register (cfr) table 22. watchdog status register - $a/$b s3 s2 s1 s0 read wdto wderr wdoff wdwo table 23. analog multiplexer control register -$c c3 c2 c1 c0 write l1ds mx2 mx1 mx0 reset value 1 000 reset condition por por, reset mode or ext_reset
analog integrated circuit device data 38 freescale semiconductor 33910 functional device operations logic commands and registers mxx - analog multip lexer input select these write-only bits selects which analog input is multiplexed to the adout0 pin according to table 24 . when disabled or when in stop or sleep mode, the output buffer is not powered and the adout0 output is left floating to achieve lower current consumption. table 24. analog multiplexer channel select configuration register - cfr this register controls the cycl ic sense timing multiplier. hvdd - hall sensor supply enable this write-only bit enables/dis ables the state of the hall sensor supply. 1 = hvdd on 0 = hvdd off cysx8 - cyclic se nse timing x 8 this write-only bit influences the cyclic sense period as shown in table 21 . 1 = multiplier enabled 0 = none mx2 mx1 mx0 meaning 0 0 0 disabled 0 0 1 reserved 0 1 0 die temperature sensor 0 1 1 vsense input 1 0 0 l1 input 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved table 25. configuration register - $d c3 c2 c1 c0 write 0 cysx8 0 0 reset value 0000 reset condition por, reset mode or ext_reset por por por
analog integrated circuit device data freescale semiconductor 39 33910 functional device operations logic commands and registers interrupt mask register - imr this register allow to mask so me of interrupt sources. the respective flags within the isr will continue to work but will not generate interrupts to the mcu. the 5v regulator over- temperature prewarning interrupt and under-voltage (vsuv) interrupts can not be masked and will always cause an interrupt. writing to the interrupt mask register (imr) will return the isr. hsm - high side interrupt mask this write-only bit enables/dis ables interrupts generated in the high side block. 1 = hs interrupts enabled 0 = hs interrupts disabled linm - lin interrupts mask this write-only bit enables/dis ables interrupts generated in the lin block. 1 = lin interrupts enabled 0 = lin interrupts disabled vmm - voltage moni tor interrupt mask this write-only bit enables/dis ables interrupts generated in the voltage monitor block. the only maskable interrupt in the voltage monitor block is the v sup over-voltage interrupt. 1 = interrupts enabled 0 = interrupts disabled interrupt source register - isr this register allows the mcu to determine the source of the last interrupt or wake-up respectively. a read of the register acknowledges the interrupt and leads irq pin to high, in case there are no other pending interrupts. if there are pending interrupts, irq will be driven high for 10s and then be driven low again. this register is also returned when writing to the interrupt mask register (imr). isrx - interrupt source register these read-only bits indicate the interrupt source following table 28 . if no interrupt is pending than all bits are 0. in case more than one interrupt is pending, than the interrupt sources are handled sequentially multiplex. table 28. interrupt sources table 26. interrupt mask register - $e c3 c2 c1 c0 write hsm -. linm vmm reset value 1111 reset condition por table 27. interrupt source register - $e/$f s3 s2 s1 s0 read isr3 isr2 isr1 isr0 interrupt source priority isr3 isr2 isr1 isr0 none maskable maskable 0 0 0 0 no interrupt no interrupt none 0 0 0 1 l1 wake-up from stop mode- highest 0 0 1 0 - hs interrupt (over-temperature) 0 0 1 1 - reserved 0 1 0 0 lin interrupt (rxshort, txdom, lin ot, lin oc) or lin wake-up 0 1 0 1 voltage monitor interrupt (low-voltage and vdd over-temperature) voltage monitor interrupt (high-voltage) 0 1 1 0 - forced wake-up lowest
analog integrated circuit device data 40 freescale semiconductor 33910 typical applications logic commands and registers typical applications the 33910 can be configured in several applications. the figure below shows the 33910 in the typical slave node application. voltage regulator spi & control reset control module lvr, hvr, htr, wd, window watchdog module lin physical layer vs2 5v output module hs1 hvdd vsense analog input module digital input module lin rxd adout0 sclk mosi miso txd cs wake up module interrupt control module lvi, hvi, hti, oci vbat sense m odule analog multiplexer l1 hs2 wdconf chip temp sense module pwmin high side control module lgnd internal bus mcu rst irq agnd pgnd vs1 agnd vdd a/d a/d sci spi timer rst vdd irq c4 c3 r7 c2 c1 d1 v r1 c6 lin r2 hall sensor supply c5 bat typical component values: c1 = 47f; c2 = c4 = 100nf; c3 = 10f; c5 = 220pf r1 = 10k ? ; r2 = 20k ? -200k ? recommended configuration of the not connected pins (nc): pin 15, 16, 17, 19, 20, 21, 22 = gnd pin 11 = open (floating) pin 28 = this pin is not internally connected and may be used for pcb routing optimization.
analog integrated circuit device data freescale semiconductor 41 33910 packaging package dimensions packaging package dimensions important for the most current revision of the package, visit www.freescale.com and select documentation, then under available documentation column select packaging information. ac suffix (pb-free) 32-pin lqfp 98ash70029a revision d
analog integrated circuit device data 42 freescale semiconductor 33910 important for the most current revision of the pack- age, visit www.freescale.com and select documenta- package dimensions (continued) ac suffix (pb-free) 32-pin lqfp 98ash70029a revision d
analog integrated circuit device data freescale semiconductor 43 33910 revision history revision history revision date description of changes 3.0 9/2007 ? initial release 4.0 2/2008 ? changed functional block diagram on page 22.
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